# JFET Drain Characteristic|What is JFET Drain Characteristic

## JFET Drain Characteristic With Ves = 0

Such a characteristic is shown in Fig. 1 and has been already discussed briefly in previous article. It can be subdivided into following four regions : Ohmic Region OA : This part of the characteristic is linear indicating that for low values of VDS, current varies directly with voltage following Ohm’s Law. It means that JFET behaves like an ordinary resistor till point A (called knee) is reached.

### Curve AB :

In this region, ID increases at reverse square law rate upto point B which is called pinch-off point. This progressive decrease in the rate of increase of ID is caused by the square law increase in the depletion region at each gate upto point B where the two regions are closest without touching each other. The drain-to-source voltage VDS corresponding to point B is called pinch-off voltage VP. But it is essential to remember that “pinch-off ” does not mean “cur- rent-off”.

### Pinch-off Region BC

It is also known as saturation region or ‘amplified’ region. Here. JFET operates as a constant-current device because ID is relatively independent of VDS. It is due to the fact that as VDS increases, channel resistance also increases proportionally thereby keeping I, practically constant at IDSS. It should also be noted that the reverse bias required by the gate-channel junction is supplied entirely by the voltage drop across the channel resistance due to flow of IDSS and none by external bias because VGS= 0.

Drain current in this region is given by Shockley’s equation

It is the normal operating region of the JFET when used as an amplifier.

### Breakdown Region

If VDS increased beyond its value corresponding to point C (called avalanche breakdown voltage), JFET enters the breakdown region where ID increases to an excessive value. This happens because the reverse-biased gate-channel P-N junction undergoes avalanche breakdown when small changes in VDS produce very large changes in ID .

It is interesting to note that increasing values of VDS make a JFET behave first as a resistor (ohmic- region), then as a constant-current source (pinch-off region) and finally, as a constant-volt- age source (breakdown region).

## JFET Characteristics With External Bias

Fig. 2 shows a family of lD versus VDS curves for different values of V as the negative gate bias voltage is increased

(i) pinch off voltage is reached at a lower value of ID than when VGS= 0.

(ii) value of VDS for breakdown is decreased. When an external bias of, say, -1V is applied between the gate and source, the P-N junctions become reverse-biased even when lD=0. Hence, the depletion regions are already formed which penetrate the channel to a certain extent.

The amount of reverse bias required to be produced by would, obviously, be decreased by 1V. In other words, a smaller voltage drop along the channel (i.e. smaller than when VGS= 0) will increase the depletion regions to the point where they will pinch off the current. Consequently, VP. is reached at a lower ID value than when VGS= 0.

Now, let us see why value of VDS for breakdown is decreased as the negative gate bias voltage is increased. It is simply due to the fact that VGS keeps adding to the reverse bias at the junction produced by current flow.

It is seen that with VGS =0, ID saturates at IDSS and the characteristic shows VGS = 4V. When an external bias of -1 V is applied, gate-channel junctions still require -4 V to achieve pinch-off (remember, VGS= -VP,). It means that a 3V drop is now required along the channel instead of the previous 4V. Obviously, this 3V drop can be achieved with a lower value of ID. Similarly, when VGS is -2V and -3V, pinch-off is achieved with 2 V and 1 V respectively along the channel.

These drops of 2 V and 1V are obtained with further reduced values of ID As seen, when VGS = -4 V (i.e. numerically equal to VP), no channel drop is required. Hence, D, is zero.

In general, VP= VDS(P)VGS , Where VDS(P) is the pinch-off value of VDS for a given value of VGS .