FET (Field Effect Transistor)|What is a FET ?

FET : What is a FET ?

The acronym FET’ stands for field effect transistor. It is a three-terminal uni-polar solid-state device in which current is controlled by an electric field as is done in vacuum tubes. Broadly speaking. there are two types of FETs :

(a) Junction field effect transistor (JFET)

(b) Metal-oxide semiconductor FET (MOSFET). It is also called Insulated-gate FET (IGFET). It may be further subdivided into:

  1. Depletion-enhancement MOSFET Le. DEMOSFET
  2. Enhancement-only MOSFET i.e. E-only MOSFET

Both of these can be either P-channel or N-channel devices.

The FET family tree is shown below :

FET Family tree e1615548816547
FET family tree

Junction FET (JFET)

(a) Basic Construction

As shown in Fig.1, it can be fabricated with either an N-channel or P-channel though N- channel is generally preferred. For fabricating an N-channel JFET, first a narrow bar of N-type semiconductor material is taken and then two P-type junctions are diffused on opposite sides of its middle part (Fig.1 (a)), These junctions form two P-N diodes or gates and the area between these gates is called channel.

The two P-regions are internally connected and a single lead is brought out which is called gate terminal. Ohmic contacts (direct electrical connections) are made at the two ends of the bar-one lead is called source terminal S and the other drain terminal D.

When potential difference is established between drain and source, current flows along the length of the ‘bar’ through the channel located between the two P-regions. The current consists of only majority carriers which, in the present case, are electrons. P-channel JFET is similar in construction except that it uses P-type bar and two N-type junctions. The majority carriers Following FET notation is worth remembering: e holes which flow through the channel located between the two N-regions or gates.

Junction FET
Fig. 1 Junction FET
  1. Source : It is the terminal through which majority carriers enter the Mr. Since carriers come from it, it is called the source.
  2. Drain : It is the terminal through which majority carriers leave the bar i.e. they are drained out from this terminal. The drain to source voltage VDS drives the drain current ID .
  3. Gate : These are two internally-connected heavily-doped impurity regions which form two P-N junctions. The gate-source voltage V GS reverse- biases the gates.
  4. Channel : It is the space between two gates through which majority carriers pass from source-to-drain when VDS is applied. Schematic symbols for N-channel and P-channel JFET are shown in Fig.1 (e). It must be kep nd that gate arrow always points to N-type material.

(b) Theory of Operation

While discussing the theory of operation of a JFET, it should be kept in mind that

  1. Gate are always reversed-biased. Hence, gate current , is practically zero.
  2. The source terminal is always connected to that end of the drain supply which provides the necessary charge carriers, In an N-channel JFET, source terminal S is connected to the negative the drain voltage supply (for obtaining electrons). In a P-channel JFET, S is connected to the positive end of the drain voltage supply for getting holes which flow through the channel.
Theory of FET e1615549303642
Fig. 2

Let us now consider an N-channel JFET and discuss its working when either Vor Vor both are changed

(i) When VGS =0 and VDS = 0

In this case, drain current ID =0, because VDS=0. The depletion regions around the P-N junctions are of equal thickness and symmetrical as shown in Fig. 2 (a)

(ii) When VGS =0 and VDS is increased from zero

For this purpose, the JFET is connected to the Vpn supply as shown in Fig. 2 (b). The electrons (which are the majority carriers) flow from S to D whereas conventional drain current ID, flows through the channel from D to S. Now, the gate-to-channel bias at any point along the channel is = |VDS|+|VGS| i.e. the numerical sum of the two voltages. In the present case, external bias VGS = 0.

Hence gate-channel reverse bias is provided by VDS alone. Since the value of VDS keeps decreasing (due to progressive drop along the channel) as we go from D to S, the gate-channel bias also decreases accordingly. It has maximum value in the drain-gate region and minimum in the source-gate region. Hence, depletion regions penetrate more deeply into the channel in the drain-gate region than in the source-gate region. This explains why the depletion regions become wedge shaped when VDS is applied (Fig. 2. (b).

As VDS is gradually increased from zero, I, increases proportionally as per Ohm’s law. It is found that for small initial values of Vas the N-type channel material acts like a resistor of constant value. It is so because Ves being small, the depletion regions are not large enough to have any significant effect on channel cross-section and, hence, its resistance. Consequently, ID increases linearly as VDS is increased from zero onwards .

The ohmic relationship between VDS and 1, continues till V reaches a certain critical value called pinch-off voltage Vro when drain current becomes constant at its maximum value called Ins The SS in IDSS indicates that the gate is shorted to source to make sure that VGS= 0. This current is also known as zero-gate-voltage drain current. It is seen from Fig. 2(c) that under pinch-off conditions, separation between the depletion regions near the drain end reaches a minimum value W. It should, however, be carefully noted that pinch-off does not mean “current-off’. In fact, ID is maximum at pinch-off.

When VDS increased beyond VPO ,ID remains constant at its maximum value IDDS upto a certain point. It is due to the fact that further increase in VDS (beyond VPO ) causes more of the channel on the source end to reach the minimum width as shown in Fig. 2 (d), It means that the channel width does not increase, instead its length L increases.

As more of the channel reaches the minimum width. the resistance of the channel increases at the same rate at which VDS increases. In other word increase in VDS neutralized by increases in RDS. Consquently, ID= (VDS/ RDS) remains unchanged even though VDS is increased. Ultimately, a certain value of VDS (called VDSO) is reached when JFET breaks down and ID increases to an excessive value as seen from drain characteristic of Fig. 5.

(ii) When VDS = 0 and VGS is decreased from zero

Fet 1
Fig. 3

In this case, as VGS is made more and more negative, the gate reverse bias increases which increases the thickness of the depletion regions. As negative value of VGS is increased, a stage comes when the two depletion regions touch each other as shown in Fig. 3. In this condition, the channel is said to be cut-off. This value of VGS which cuts off the channel and hence the drain current is called VGS(off).

It may be noted that VGS(off) = -VPO OR |VPO |=|VGS(off)| . As seen from Fig. 6 because VPO = 4 V, VGS(off) =-4 V. Obviously, their absolute values are equal.

(iv) When Vs is negative and V Ds

As seen from Fig. 6, as VGS is made more and more negative, values of VP as well as breakdown voltage are decreased.

Fet e1615549435456
Fig. 4

(c) Summary

Summarizing the above, we have that

  1. Keeping VGS at a fixed value (either zero or negative), as VDS is increased, ID initially increases till channel pinch-off when it becomes almost constant and finally increases excessively when JFET breaks down under high value of VDS . As VGS is kept fixed at progressively higher negative values, the values of VP as well as breakdown voltage decrease.
  2. Keeping Vps at a fixed value, as VGS is made more and more negative, ID decreases till it is reduced to zero for a certain value of VGS called VGS(off) .

Since gate voltage controls the drain current, JFET is called a voltage-controlled device. A P- channel JFET operates exactly in the same manner as an N-channel JFET except that current carriers are holes and polarities of both VDD and VGS are reversed.

Since only one type of majority carrier (either electrons or holes) is used in JFETS, they are called uni-polar devices unlike bipolar junction transistors (BJTS) which use both electrons and holes as carriers.

Static Characteristics of a JFET

We will consider the following two characteristics:

  1. Drain characteristic : It gives relation between ID and VDS for different values of VGS (which is called running variable).
  2. Transfer characteristic : It gives relation between ID and VGS for different values of VDS .

We will analyse these characteristics for an N-channel JFET connected in the common-source mode as shown in Fig. 4. We will first consider the drain characteristic when VGS= 0 and then when VGS has any negative value upto VGS(off) .

FET Applications

FETS can be used in almost every application in which bipolar transistors can be used. However, they have certain applications which are exclusive to them:

  1. As input amplifiers in oscilloscopes, electronic voltmeters and other measuring and testing equipment because their high r reduces loading effect to the minimum.
  2. In logic circuits where it is kept OFF when there is zero input while it is turned ON with very little power input.
  3. For mixer operation of FM and TV receivers.
  4. As voltage-variable resistor (VVR) in operational amplifiers and tone controls etc.
  5. Large-scale integration (LSI) and computer memories because of very small size.

Advantages of FET

FETS combine the many advantages of both BJTS and vacuum tubes. Some of their main advantages are:

1. High input impedance,

2. Small size,

3. Ruggedness,

4. Long life,

5. High frequency response,

6. Low noise,

7. Negative temperature coefficient, hence better thermal stability,

8. High power gain,

9, A high immunity to radiations,

10. No offset voltage when used as a switch (or chopper),

11. Square law characteristics.

The only disadvantages are:

1. Small gain-bandwidth product,

2. Greater susceptibility to damage in handling them.

What is a FET ?

The acronym FET’ stands for field effect transistor. It is a three-terminal uni-polar solid-state device in which current is controlled by an electric field as is done in vacuum tubes. Broadly speaking. there are two types of FETs :
(a) Junction field effect transistor (JFET)
(b) Metal-oxide semiconductor FET (MOSFET). It is also called Insulated-gate FET (IGFET). It may be further subdivided into:
Depletion-enhancement MOSFET Le. DEMOSFET
Enhancement-only MOSFET i.e. E-only MOSFET
Both of these can be either P-channel or N-channel devices.

What is theory of operation ?

While discussing the theory of operation of a JFET, it should be kept in mind that
1. Gate are always reversed-biased. Hence, gate current , is practically zero.
2. The source terminal is always connected to that end of the drain supply which provides the necessary charge carriers, In an N-channel JFET, source terminal S is connected to the negative the drain voltage supply (for obtaining electrons). In a P-channel JFET, S is connected to the positive end of the drain voltage supply for getting holes which flow through the channel.
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What is static characteristics of a JFET ?

We will consider the following two characteristics:
1. Drain characteristic : It gives relation between ID and VDS for different values of VGS (which is called running variable).
2. Transfer characteristic It gives relation between ID and VGS for different values of VDS .
We will analyse these characteristics for an N-channel JFET connected in the common-source mode as shown in Fig. 4. We will first consider the drain characteristic when VGS= 0 and then when VGS has any negative value upto VGS(off) .
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What is advantages and disadvantages of FET ?

FETS combine the many advantages of both BJTS and vacuum tubes. Some of their main advantages are:
1. High input impedance,
2. Small size,
For more Click hare

What is the applications of FET ?

FETS can be used in almost every application in which bipolar transistors can be used. However, they have certain applications which are exclusive to them:

1. As input amplifiers in oscilloscopes, electronic voltmeters and other measuring and testing equipment because their high r reduces loading effect to the minimum.
2. In logic circuits where it is kept OFF when there is zero input while it is turned ON with very little power input.

For more click hare

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